The present inventors previously proposed processes for producing a thin copper foil-clad circuit board substrate in, for example, JP-A-2-60189, JP-A-2-25090, JP-A-2-25089, JP-A-2-22896, JP-A-2-22887 and JP-A-2-97688. (The term "JP-A" as used herein means an "unexamined published Japanese patent application".)
These processes enable the industrial production of thin copper foil-clad circuit board substrates having high thickness precision. However, a close examination of the surfaces of the copper foils in thin copper foil-clad circuit board substrates obtained by these processes has revealed that there are projections of several micrometers or smaller which are unevenly distributed over the surface.
Such projections have been observed even on the copper foil surfaces of thin copper foil-clad circuit board substrates produced using copper foil-clad circuit board substrates of the best quality. The cause of this was investigated and, as a result, it has been ascertained that even such a high-quality copper foil-clad circuit board substrate has adherent dust particles on the copper foil surface thereof, which mainly comprise resin powder particles and have an average particle diameter of from 3 to 10 .mu.m in most cases and which are unevenly distributed over the surface, and that at least part of these adherent dust particles function as a resist during the etching of the whole copper foil surface to form the projections.
Although such projections do not substantially give an adverse influence in the formation of conventional circuits, particularly in the case of forming fine circuit patterns, there have been the problems that the resist on the projection becomes thinner than other portion or since the adhesion is poor, the resist peels off at etching and the copper foil at that portion is removed. Thus, the projections become a cause of defect development.